During the processing of semiconductor devices, alignment structures, e.g., scribe line marks (SLMs), utilize a vertical step in a silicon wafer to obtain the location of an alignment structure and to align it to a stepper/scanner. However, obtaining the location of the alignment structure in conventional FinFET structures, having a single trench, is difficult because the conventional FinFET process leaves either a “sea-of-fins” or a deep trench. As a result, the stepper/scanner has difficulty recognizing the alignment structure as it requires large areas with different silicon heights.
A need therefore exists for methodology for fabricating semiconductor devices with improved alignment features, and the resulting device.